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d a t a sh eet preliminary speci?cation file under integrated circuits, ic14 1995 mar 30 integrated circuits philips semiconductors PCA8516 stand-alone osd
1995 mar 30 2 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 contents 1 features 2 general description 3 ordering information 4 block diagram 5 pinning information 5.1 pinning 5.2 pin description 6 serial i/o 6.1 i 2 c-bus serial interface 6.2 high-speed serial interface (hio) 7 character fonts 7.1 character font address map 7.2 character font rom 8 display ram organization 8.1 description of display ram codes 8.2 loading character data into display ram 8.3 writing character data to display ram 9 commands 9.1 command 0 9.2 command 1 9.3 command 2 9.4 command 3 9.5 command 4 9.6 command 5 9.7 command 6 9.8 command 7 9.9 command 8 9.10 command 9 9.11 command a 9.12 commands b, c and d 9.13 command e 9.14 command f 9.15 command g 10 miscellaneous 10.1 space and carriage return codes in different background/shadowing modes 10.2 combination of character font cells 11 osd clock 12 osd clock selection for different tv standards 12.1 osd frequency 12.2 maximum number of characters per row 12.3 maximum number of rows per frame 13 output ports 13.1 mask options 14 default values after power-on-reset 15 limiting values 16 dc characteristics 17 ac characteristics 18 package outlines 19 soldering 19.1 introduction 19.2 dip 19.3 so 20 definitions 21 life support applications 22 purchase of philips i 2 c components
1995 mar 30 3 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 1 features display ram: 256 13 bits display character fonts: 253 (fixed in rom, mask programmable) starting position of the first character displayed: 64 vertical and 64 horizontal starting positions can be selected by software character size: 4 different character sizes on a line-by-line basis (1 dot = 1h/1v; 2h/2v; 3h/3v and 4h/4v) character matrix: 12 18 with no spacing between characters and no rounding function foreground colours: 16 combinations of red, green, blue and intensity on character-by-character basis background/shadowing modes: 4 modes available, no background, box shadowing, north-west shadowing and frame shadowing (raster blanking) on frame basis background colours: 16 combinations of red, green, blue and intensity on word-by-word basis. available when background mode is in either the box shadowing, north-west shadowing or frame shadowing mode osd oscillator: on-chip phase-locked loop (pll) character blinking ratio: 1 : 1, 1 : 3 and 3 : 1 (programmable frequency of 1 16 , 1 32 , 1 64 or 1 128 of f vsync ) on character basis display format: flexible display format by using the carriage return code, maximum number of characters per line is also flexible and depends upon the osd clock frequency spacing between lines: 4 choices comprising 0, 4, 8 and 12 horizontal scan lines display character ram address auto-post-increment when writing data fast i 2 c-bus serial interface (400 kbaud) or high-speed 3-wire serial interface (1 mbaud) for data/command transfer acm (active character monitor) specifically for use in camcorder applications on word basis; can also be used as a 5th colour control with r, g, b and i signals programmable active input polarity of hsync and vsync programmable output polarity of r, g, b, i and fb supply voltage: 5 v 10% operating temperature: - 20 to +70 c package: sdip24 or so24. 2 general description the PCA8516 is a member of the pca85xx cmos family and is an on-screen character display generator controlled by a microcontroller via the on-chip fast i 2 c-bus interface or the on-chip high-speed 3-wire serial interface. it is suitable for use in high-end tv or camrecorder applications and has also been designed for use in conventional mid-end tv with advanced graphic features. 3 ordering information type number package name description version PCA8516p sdip24 plastic shrink dual in-line package; 24 leads (400 mil) sot234-1 PCA8516t so24 plastic small outline package; 24 leads; body width 7.5 mm sot137-1
1995 mar 30 4 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 4 block diagram a ndbook, full pagewidth control register display character ram address buffer selector display rom display control and output stage instruction decoder scl/sclk sda/sin control signals i/o port buffers character size register/ control crystal oscillator vsync c xtal1(in) xtal2(out) write address counter horizontal position register/ counter vertical position register/ counter internal synchronous circuit pll oscillator v v external/internal data switching buffer csync separation hsync vsync hsync p00 p01 p04/acm (vob2) i(vow3) r(vow0) g(vow1) b(vow2) fb(vob) acm(vob2) reset testing circuitry test1 test2 ti00 to ti11 12 i c slave receiver or high-speed i/o receiver 2 mlc347 dd av dd av ss ss e hio/ i c 3 2 fig.1 block diagram.
1995 mar 30 5 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 5 pinning information 5.1 pinning fig.2 pin configuration for sdip24. handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 mlc927 i (vow3) p04/acm (vob2) test2 test1 vsync hsync sda/sin sck/sclk xtal1 (in) xtal2 (out) v ss reset e r (vow0) p00 g (vow1) p01 b (vow2) fb (vob) av dd v dd av ss hio/i c c PCA8516 2
1995 mar 30 6 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 5.2 pin description table 1 sdip24 and so24 packages symbol pin i/o description i (vow3) 1 o character output signal for intensity control. p04/acm (vob2) 2 o port 04 output or active character monitor output (vob2). test2 3 i test mode selection; for normal operation test2 is connected to v ss . test1 4 i test mode selection; for normal operation test1 is connected to v ss . c 5 i/o capacitor connection for on-chip osd pll oscillator. vsync 6 i vertical synchronization input, active polarity programmable. hsync 7 i horizontal synchronization input, active polarity programmable. sda/sin 8 i/o data line of the i 2 c-bus interface or the data line for the high-speed serial interface. scl/sclk 9 i/o clock line of the i 2 c-bus interface or the clock line for the high-speed serial interface. xtal1 (in) 10 i system clock input. xtal2 (out) 11 o system clock output. v ss 12 i ground, digital. reset 13 i master reset input (active low). e 14 i chip enable (active high) for the high-speed serial interface. when the i 2 c-bus interface is selected this pin should be connected to v ss . hio/i 2 c 15 i serial interface selection. when this pin is low the high-speed serial interface is selected; when this pin is high the i 2 c-bus interface is selected. r (vow0) 16 o character output signal: vow0 for red. p00 17 i/o general purpose i/o port 00. g (vow1) 18 o character output signal: vow1 for green. p01 19 i/o general purpose i/o port 01. b (vow2) 20 o character output signal: vow2 for blue. v dd 21 i power supply, digital. fb (vob) 22 o fast blanking output (vob). av ss 23 i ground, analog. av dd 24 i power supply, analog.
1995 mar 30 7 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 6 serial i/o the PCA8516 has two means by which it can communicate with a microcontroller: a fast i 2 c-bus serial interface and a high-speed serial interface. selection of either interface is achieved via pin 15, hio/i 2 c. when hio/i 2 c is low, the hio serial interface is selected. when hio/i 2 c is high, the i 2 c-bus serial interface is selected. the PCA8516 is programmed by a series of commands sent via one of these interfaces. there are 16 commands; each command selecting different functions of the PCA8516. the 16 commands are described in detail in chapter 9. 6.1 i 2 c-bus serial interface the i 2 c-bus serial interface is selected by driving pin 15 ( hio/i 2 c) high. data transmission conforms to the fast i 2 c-bus protocol; the maximum transmission rate being 400 khz. the PCA8516 operates in the slave receiver mode and therefore in normal operation is write only from the master device. the format of the data streams sent via the i 2 c-bus interface is shown in fig.3. the first data byte is the slave address 1011 101x b . the last bit of the slave address is always a logic 0, except in the test mode when it could be a logic 1. subsequent data bytes contain the commands for control of the device. upon the successful reception of a complete data byte by the shift register, an acknowledge bit is sent. a stop condition terminates the data transfer operation. the i 2 c-bus interface is reset to its initial state (waiting for a slave address call) by the following conditions: after a master reset after a bus error has been detected on the i 2 c-bus interface. under both these conditions the data held in the shift register is abandoned. 6.1.1 m aximum speed of the i 2 c- bus the maximum i 2 c-bus transmission rate that the pce8515 can receive is 400 khz. however, if the data byte being transmitted is for display ram then internal synchronization of the write operation from the shift register to the display ram location is necessary. this will reduce the maximum transmission speed. the synchronization process is carried out by on-chip hardware and takes place during the hsync retrace period when vsync is inactive. the i 2 c-bus clock is pulled low if a complete display ram data byte is received before hsync becomes active. the i 2 c-bus clock will be released when hsync becomes active and then the contents of the shift register will be written into the display ram location. 6.2 high-speed serial interface (hio) the high-speed serial interface is selected when pin 15 ( hio/i 2 c) is pulled low. the high-speed serial interface has a 3-wire communication protocol; the maximum transmission rate being 1 mhz. the interface protocol is illustrated in fig.4 and described below. 1. pin 14 (e) the chip enable pin is driven high. this low-to-high transition clears the shift register and resets the serial input circuit. 2. on the first high-to-low transition of sclk after the interface has been enabled, the first data bit (d0) must be present at the sin pin. 3. on the following low-to-high transition of sclk, the first data bit (d0) will be latched into the shift register. 4. on the next high-to-low transition of sclk the second data bit (d1) must be present at the sin pin. data bit (d1) will be latched into the shift register on the following low-to-high transition of sclk. 5. the operation specified in step 4 above is repeated another 6 times, thus loading the shift register with a complete data byte. this data byte is then transferred to the command interpreter which takes the appropriate action. 6. providing the chip enable signal remains high, a 2nd data byte can be transferred. the 1st data bit of the next data transfer takes place on the falling edge of the sclk signal. the following points should be noted: if the chip enable signal is pulled low at any time the shift operation in progress is stopped and the hio slave receiver is disabled the rising edge of the chip enable signal resets the hio slave receiver.
1995 mar 30 8 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.3 i 2 c-bus write timing diagram - data stream. handbook, full pagewidth s slave address ack ack 8 7 08 7 0 1st data byte 2nd data byte 0 1 1 1 1 0 0 nth data byte w ack 8 7 0 ack 8 07 p bit 0 mra818 lsb msb bs i c-bus bit stream 2 o bit 7 command register data fig.4 high-speed i/o format. handbook, full pagewidth mlb395 - 1 t s rising edge of sclk sin sampled t h falling edge of sclk d changes (from hio master and connected to sin pin of hio slave) t s d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 sin sclk e d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 out sclk d out (1) t s 3 1 m s; t h 3 1 m s.
1995 mar 30 9 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 7 character fonts 256 character fonts may be held in rom; 253 customer selected fonts and three reserved character font codes. customer selected fonts are mask programmable. each character font is stored in a 12 19 dot matrix, as shown in fig.5. elements in rows 1 to 18 can be selected as visible dots on the screen; row 0 is used only for the combination of two characters in a vertical direction, when the north-west shadowing mode is selected (see sections 9.9 and 10.2). extremely high resolution can be achieved by having no spacing between characters on the same line and by programming the inter-line spacing to zero. the 12 18 dot matrix is suitable for the display of semigraphic patterns, kanji, hiragana, katagana or even chinese characters. 7.1 character font address map figure 6 shows the character font address map in rom and ram. addresses ffh and feh hold the reserved codes for space and carriage return functions respectively; address fdh is reserved for testing purposes and addresses (00h to fch) contain the character font codes. 7.2 character font rom rom is divided into two parts: rom1 and rom2. the organization of the bit patterns stored in rom1 and rom2 is shown in fig.7. the file format to submit to philips for customized character sets is also shown in fig.7. the following points should be noted: 1. row 0 of each font is reserved for vertical combination of two fonts. 2. when two font cells are combined in a vertical direction row 0 of the lower font must contain the same bit pattern as held in row 18 of the character above it. 3. binary 1 denotes visual dots; binary 0 denotes a blank space. 4. rom1 and rom2 data files are in intel hex format on a byte basis. each byte is structured high nibble followed by low nibble. 5. the remaining unused 16 bytes (one character font) in rom1/rom2 must be filled with ffh. 6. cs denotes checksum. a software package (osdgem) that assists in the design of character fonts on-screen and that also automatically generates the bit pattern hex files, is available on request. the package is run under the ms-dos environment for ibm compatible pcs. fig.5 character dot matrix organization. 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 mlc350 fig.6 rom address map. 0 253 (fdh) 254 (feh) 255 (ffh) mask programmable font carriage return code space code reserved code mlb344 test code 252 (fch)
1995 mar 30 10 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.7 character font pattern stored in rom1 and rom2. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 column row lsb msb rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 0 0 0 2 2 0 3 f c 2 2 0 2 2 0 3 f f 0 0 1 5 5 2 0 0 c 0 3 0 0 0 0 2 2 0 3 f c 2 2 0 2 2 0 3 f f 0 0 1 5 5 2 0 0 c 0 3 0 rom1 rom2 3 f c 2 2 0 2 2 0 3 f c 2 2 0 0 0 1 5 5 3 0 0 6 0 5 8 3 f c 2 2 0 2 2 0 3 f c 2 2 0 0 0 1 5 5 3 0 0 6 0 5 8 rom1 : 1 0 0 0 0 0 0 0 00 00 22 fc 03 22 20 f2 3f 01 20 55 0c 00 03 : 1 0 0 0 1 0 0 0 < - - - data for font 2 - - - > : 1 0 0 0 2 0 0 0 < - - - data for font 3 - - - > rom2 : 1 0 0 0 0 0 0 0 fc 03 22 20 c2 3f 20 12 00 53 65 00 58 : 1 0 0 0 1 0 0 0 < - - - data for font 2 - - - > : 1 0 0 0 2 0 0 0 < - - - data for font 3 - - - > byte # __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ 0 1 2 3 4 5 6 7 8 9 a b c d e f f f c s f f c s f f c s f x ff ff c s f 0 ff ff c s f x ff ff c s mlb345 1110987 6543210
1995 mar 30 11 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 8 display ram organization the display ram is organized as 256 13 bits. the general format of each ram location is as follows. bits <12-5> hold character data and allow a choice from 253 customer designed character fonts to be selected or one of three reserved codes. bits <4-0> contain the attributes of the character font, for example colour, character size etc. 8.1 description of display ram codes there are four data formats for display ram code: 1. character font code 2. test code 3. carriage return code 4. space code. the above data formats allow great flexibility in the creation of on screen displays; see fig.8. 8.1.1 c haracter font code if bits <12-5> are in the range (00h to fch), then this is a character font code. 1 of 253 customer designed character fonts can be selected. bits <4-1> determine the colour of the character, a choice of 16 colours being available. bit <0> determines whether the character blinks or not. the format of the character font code is shown in table 2. 8.1.2 t est code if bits <12-5> hold fdh, then this is a special code reserved for testing purposes only. 8.1.3 c arriage return code if bits <12-5> hold feh, then this is the carriage return code. a transparent pattern will be displayed on the screen and the next character will be displayed at the beginning of the next line. bits <4-3> select the size of the characters to be displayed on the next line. bits <2-1> determine the spacing between lines of displayed characters. bit <0> is the end of display bit and indicates the end of display of the current screen before exhaustion of display ram (i.e. before the 256th ram location). the format of the carriage return code is shown in table 3. 8.1.4 s pace code if bits <12-5> hold ffh, then this is the space code. a transparent pattern, equal to one character width, will be displayed on the screen. a mask programmable option is available that allows the space character to be transparent or to have a programmable background colour; see section 13.1. bits <4-1> determine the background colour of the characters that follow the space code in both the box shadowing and north-west shadowing modes. bit <0> is the active character monitor (acm) enable/disable bit. the acm signal is specifically for use in camrecorder applications where part of the display is to be recorded on tape and displayed on the screen, whilst the remaining part is for display only. figure 9 shows a typical acm application. during the back-tracing period r, g, b, i, fb and acm are inactive. the format of the space code is shown in table 4. table 2 format of character font code table 3 format of carriage return code table 4 format of space code 121110987654321 0 c7 c6 c5 c4 c3 c2 c1 c0 t4 t3 t2 t1 t0 character font code (00h - fch) foreground colour blink 1211109876543210 c7 c6 c5 c4 c3 c2 c1 c0 t4 t3 t2 t1 t1 carriage return code (feh) character size line spacing end 121110987654321 0 c7 c6 c5 c4 c3 c2 c1 c0 t4 t3 t2 t1 t0 space code (ffh) background colour acm
1995 mar 30 12 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.8 example of on screen display. handbook, full pagewidth vstart hstart volume channel cr t h e n e w f u n c i o n t i n p c a 8 5 1 0 sp cr cr cr e l c o m e w cr cr st a ndal hi ! t h is i s sp sp cr line spacing 1 = 4h line spacing 2 = 8h line spacing 3 = 0h line spacing 4 = 0h line spacing 6 = 0h sp four different background colours (in box shadowing mode): black red green blue line spacing 4 = 4h sp mra832
1995 mar 30 13 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.9 example of acm signal for use in camrecorder applications. handbook, full pagewidth made by mos ic taiwan, philips battery status : ok shutter speed : 500 focal length : 28 mm in this example, all the characters are displayed on the viewfinder. as only the data 'date : july 15, 1994' is to be recorded onto the tape, only these characters' acm attribute bit is set to a logic 1. philips mra831 date : july 15, 1994
1995 mar 30 14 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 8.2 loading character data into display ram three registers are used to address and load data into the display ram. these registers are described below. 8.2.1 dcr a ddress r egister (dcrar) table 5 dcr address register this register holds the address of the location in display ram into which data is to be written. command 3 loads the high nibble of the address into this register; command 4 loads the low nibble of the address. 8.2.2 dcr a ttribute r egister (dcrtr) table 6 dcr attribute register the attribute register is loaded with character font attribute data using command 2. the data will be loaded into bits <4-0> of the location in ram addressed by the contents of dcrar. bits 7 to 5 are not used and are reserved. 8.2.3 dcr c haracter r egister (dcrcr) table 7 dcr character register this register holds the character font data loaded by command 1. the data will be loaded into bits <12-5> of the location in ram addressed by the contents of dcrar. 76543210 a7 a6 a5 a4 a3 a2 a1 a0 76543210 --- t4 t3 t2 t1 t0 76543210 c7 c6 c5 c4 c3 c2 c1 c0 8.3 writing character data to display ram the procedure for writing character data to the display ram is as follows: 1. select the start address in display ram. the start address can take any value between 0 and 255. command 3 is used to load the high nibble of the start address. command 4 is used to load the low nibble of the start address. the start address is stored in dcrar. 2. load the character attributes into dcrtr using command 2. the actual attribute selected is dependent upon whether the character font code, carriage return code or space code has been selected by command 1 (see section 8.1). if the attributes of a series of displayed characters are the same, the contents of this register need not be updated. 3. load the character font data into dctcr using command 1 or command 5. either of these commands signal that a complete command byte is available and the data held in registers dcrtr and dcrcr is loaded into the ram location pointed to by the address stored in dcrar. the address held in dcrar is then incremented by 1 pointing to the next ram location in anticipation of the next operation. a description of all the commands is given in chapter 9.
1995 mar 30 15 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 9 commands the PCA8516 is programmed by a series of commands sent by a microcontroller via the i 2 c-bus interface or the high-speed serial interface. 17 commands (commands 0 to g) are available for selecting the various functions of the PCA8516. a command overview is shown in table 8; full descriptions of each command are given in sections 9.1 to 9.15. table 8 command overview (note 1) note 1. x denotes dont care state. command bs1 bs0 7 6543210 0 command bank selection x x 0 11110bs1bs0 1 character font selection - bank 1 0 0 1 c6 c5 c4 c3 c2 c1 c0 2 character attributes x 0 0 0 0 t4 t3 t2 t1 t0 3 display character address high 0 0 0 0 1 0 a7 a6 a5 a4 4 display character address low 0 0 0 0 1 1 a3 a2 a1 a0 5 character font selection - bank 2 1 0 1 c6 c5 c4 c3 c2 c1 c0 6 osd pll oscillator divisor 0 1 0 0 d5 d4 d3 d2 d1 d0 7 scan mode, polarity of fb, acm, r, g, b and i; osd enable/disable 0 1 0 1 0 0 m1 m0 bp en 8 polarity of hsync and vsync, display mode 0 1 0 1 0 1 hp vp s1 s0 9 blinking frequency, blinking frequency active ratio 0 1 0 1 1 0 bf1 bf0 br1 br0 a i/o port selection 0 1 0 1110a/p00 b vertical start position high 0 1 1 0 0 1 v5 v4 v3 v2 c vertical start position low/ horizontal start position high 0 1 1 0 1 0 v1 v0 h5 h4 d horizontal start position low 0 1 1 0 1 1 h3 h2 h1 h0 e write to ports p00, p01 and p04 0 1 1 1 x p04 x x p01 p00 f background colour in frame shadowing mode 0 0 0100rgbi g enable/disable osd horizontal stabilization circuit (regen h), selection of half-tone background mode and character size of first line 0 0 0 1 0 1 hm3 ht2 fs1 fs0
1995 mar 30 16 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 9.1 command 0 table 9 command 0 format command 0 is used to select the command bank. bits bs1 and bs0 are the two flags that indicate the current command bank being executed. during a master reset these two bits are cleared (bs1 = 0, bs0 = 0). each command has its own associated command bank, this is shown in table 8. 9.2 command 1 table 10 command 1 format command 1 is used to load character data into the dcr character register. the data will specify either a character font code, the test code, the carriage return code or the space code. these codes are explained in detail in section 8.1. 9.3 command 2 table 11 command 2 format this command writes character attribute data into the dcr attribute register. the actual character attribute is dependent upon the code selected by command 1. see the data formats shown in tables 2, 3 and 4. 76543210 0 1 1 1 1 0 bs1 bs0 bs1bs076543210 0 0 1 c6c5c4c3c2c1c0 bs1bs076543210 x 0 0 0 0 t4t3t2t1t0 9.3.1 c haracter f ont c ode attributes command 2 when used in conjunction with a character font code (80h to fch) will select 1 of 16 foreground colours and enables/disables the blinking function. table 12 selection of foreground colour table 13 selection of blinking function t4 t3 t2 t1 rgb i 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 t0 blinking 0 off 1on
1995 mar 30 17 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 9.3.2 c arriage r eturn c ode attributes command 2 when used in conjunction with the carriage return code (feh) determines the size of characters to be displayed on the next line, sets the spacing between lines of characters and enables/disables the display. the character size is also a function of the tv scanning standard being used and f osd ; this is explained in chapter 12. table 14 selection of character size table 15 selection of line spacing table 16 end of display control 9.3.3 s pace c ode attributes command 2 when used in conjunction with the space code (ffh) selects the background colour of characters in box shadowing or north-west shadowing modes and also controls the active character monitor pin. the acm pin will remain active until a space code is received that resets the acm bit to logic 0. the acm timing diagram is shown in fig.10. t4 t3 character dot size 0 0 1h/1v (the default size) 0 1 2h/2v 1 0 3h/3v 1 1 4h/4v t2 t1 line spacing (between two rows) 0 0 0h line 0 1 4h line 1 0 8h line 1 1 12h line t0 display control 0 continue to display next character. this is also the default setting. 1 end of display. table 17 selection of background colour table 18 acm control t4 t3 t2 t1 rgb i 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 t0 acm pin 0 the acm pin is inactive; this is also the default setting. 1 the acm function is active for all characters displayed following this space code.
1995 mar 30 18 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.10 r, g, b, i - acm timing. handbook, full pagewidth r g b i fb acm 's' : red 'i' : green 'z' : green + blue + intensity 'e' : blue + intensity 1st sp code : acm = on 2nd sp code: acm = off mra830 - 1 0 18 sp code sp code
1995 mar 30 19 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 9.4 command 3 table 19 command 3 format command 3 loads the dcr address register with the 4 msbs of the ram address to which data will be written. 9.5 command 4 table 20 command 4 format command 4 loads the dcr address register with the 4 lsbs of the ram address to which data will be written. 9.6 command 5 table 21 command 5 format command 5 is used to load character data into the dcr character register. the data will specify either a character font code, the test code, the carriage return code or the space code. these codes are explained in detail in section 8.1. 9.7 command 6 table 22 command 6 format command 6 loads the programmable 6-bit counter of the osd clock oscillator. the output frequency (f osd ) is a function of the decimal value of the 6-bits loaded in by command 6; see chapter 11. bs1bs076543210 0 0 0 0 1 1 a7 a6 a5 a4 bs1bs076543210 0 0 0 0 1 1 a3 a2 a1 a0 bs1bs076543210 1 0 1 c6c5c4c3c2c1c0 bs1bs076543210 0 1 0 0 d5 d4 d3 d2 d1 d0 9.8 command 7 table 23 command 7 format this command loads control register 1 with data that selects the scanning mode, the output polarity of signals fb, acm, r, g, b and i, and also enables/disables the osd clock. with reference to the scanning modes: 1v/2v is the conventional ntsc or pal scanning mode; 1v/2h is the line progress scan used for the idtv in ntsc and 2v/2h is for the pal system and is known as 50 hz to 100 hz scan conversion. table 24 selection of scanning mode table 25 selection of output polarity (see fig.13) table 26 osd clock control bs1bs076543210 0 1 0 1 0 0 m1 m0 bp en m1 m0 scan mode 0 0 1v/1h; ntsc 525lpf/60 hz or pal 625lpf/50 hz; see fig.11. this is the default setting. 0 1 reserved 1 0 1v/2h; ntsc 1050lpf/60 hz; see fig.11. 1 1 2v/2h; pal 1250lpf/100 hz; see fig.12. bp output polarity (fb, acm, r, g, b, i) 0 active low 1 active high (the default setting) en osd clock 0 disabled (the default setting) 1 enabled
1995 mar 30 20 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 handbook, full pagewidth 262.5 lines 262.5 lines vsync hsync (a) conventional ntsc 1v/1h vsync hsync 525 lines 525 lines (b) ntsc 1v/2h mra834 f = 15734 hz hsync f = 31468 hz hsync f = 60 hz vsync f = 60 hz vsync f = 60 hz vsync f = 60 hz vsync fig.11 ntsc scan formats. handbook, full pagewidth 312.5 lines vsync hsync (a) conventional pal 1v/1h vsync hsync (b) pal 2v/2h 312.5 lines 312.5 lines 312.5 lines 312.5 lines mra835 312.5 lines f = 15625 hz hsync f = 31250 hz hsync f = 50 hz vsync f = 50 hz vsync f = 100 hz vsync f = 100 hz vsync f = 100 hz vsync f = 100 hz vsync fig.12 pal scan formats.
1995 mar 30 21 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 handbook, full pagewidth fb (acm or r, g, b or i ) bp = 0 (active low) fb (acm or r, g, b or i ) bp = 1 (active high) active period active period mra836 fig.13 active levels of fb, r, g, b, and i signals. handbook, full pagewidth hsync/vsync hp/vp = 0 (active low) hsync/vsync hp/vp = 1 (active high) active period active period mra837 fig.14 active levels of hsync and vsync signals.
1995 mar 30 22 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 9.9 command 8 table 27 command 8 format command 8 loads control register 2 with data that selects the input polarity of hsync and vsync (see fig.14) and also selects the display modes. table 28 selection of input polarity of hsync/vsync table 29 selection of display mode bs1bs076543210 0 1 0 1 0 1 hp vp s1 s0 hp/vp input polarity 0 active low (the default setting) 1 active high s1 s0 display mode 0 0 mode 0: this is the no background mode. the osd characters are superimposed on the tv video signals (see fig.15). 0 1 mode 1: this is the north-west shadowing mode; available only with character sizes 2v/2h or 4v/4h. the shadows are generated as if a light source was placed north-west of the character (see figs 16 to 18). the shadows generated lie within 18 rows in a vertical direction but can be extended by one bit to the next characters first column, in a horizontal direction (see figs 19 and 20). 1 0 mode 2: this is the box shadowing mode. a background dot matrix of 12 18 bits surrounds the character font; see figs 21 and 22. 1 1 mode 3: this is the frame shadowing (raster blanking) mode. a background colour ?lls the whole screen when no bit patterns are being displayed (see fig.23). 1 of 16 background colours can be selected using command f; the default background colour is blue. 9.10 command 9 table 30 command 9 format this command loads control register 3 with data that controls both the character blinking frequency and the active ratio of the character blinking frequency. figures 25 to 29 show how blinking influences the display in different display modes. table 31 selection of blinking frequency table 32 selection of active ratio of character blinking bs1 bs0 7 6 5 4 3 2 1 0 0 1 0 1 1 0 bf1 bf0 br1 br0 bf1 bf0 blinking frequency (hz) 00 ; this is the default setting 01 10 11 br1 br0 active ratio 0 0 3 : 1 (the default setting) 0 1 1:1 1 0 1:3 1 1 reserved f vsync 16 ---------------- - f vsync 32 ----------------- f vsync 64 ----------------- f vsync 128 -----------------
1995 mar 30 23 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 handbook, full pagewidth mos 'm' : red + blue + intensity 'o' : blue 's' : red + green + intensity bp = 1 fb sp code sp code r g b i mlb346 scan line sp code fig.15 mode 0: no background mode.
1995 mar 30 24 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 handbook, full pagewidth : background fb r g b i 1f 1st character: green 2nd character: green + blue + intensity background: red + blue bp = 1 (active high) available only in character sizes 2v/2h or 4v/4h. mra839 scan line osd fig.16 mode 1: north-west shadowing mode.
1995 mar 30 25 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.17 example of north-west shadowing mode - size 2v/2h. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 1v 1h mra842
1995 mar 30 26 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.18 example of north-west shadowing mode - size 4v/4h. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 2v 2h mra843
1995 mar 30 27 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.19 example of north-west shadowing mode. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 character designed in character rom character displayed on tv screen mra844
1995 mar 30 28 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.20 north-west shadowing. handbook, full pagewidth 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0123456789101101234567891011 mra846 two characters designed in character rom separately two characters displayed on tv screen
1995 mar 30 29 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 handbook, full pagewidth background colour column 11 row 0 row 17 mra840 column 0 fig.21 mode 2: box shadowing mode.
1995 mar 30 30 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.22 example of box shadowing mode. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 size = 1 size = 2 size = 3 size = 4 mra847
1995 mar 30 31 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 handbook, full pagewidth background: blue mra841 fig.23 mode 3: frame shadowing mode.
1995 mar 30 32 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.24 timing diagram of character blinking frequency and blinking ratio. handbook, full pagewidth vsync vsync 01 23 78 1011 60 hz 14 15 01 23 78 1011 60 hz 14 15 blinking frequency: blinking ratio: 1 : 3 blinking frequency: blinking ratio: 1 : 1 blinking frequency: blinking ratio: 3 : 1 blinking frequency: blinking ratio: 1 : 3 blinking frequency: blinking ratio: 1 : 1 blinking frequency: blinking ratio: 3 : 1 mra848 f 16 vsync f 16 vsync f 16 vsync f 32 vsync f 32 vsync f 32 fig.25 blinking in no background mode. mlb397 character on character off cr code sp code cr code sp code
1995 mar 30 33 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.26 blinking in north-west shadowing mode. mlb398 character on character off cr code sp code cr code sp code fig.27 blinking in box shadowing mode (space code with background). mlb399 character on character off cr code cr code sp code sp code
1995 mar 30 34 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.28 blinking in box shadowing mode (space code without background). mlb400 character on character off cr code sp code cr code sp code fig.29 blinking in frame shadowing mode. mlb401 character on character off cr code sp code cr code sp code
1995 mar 30 35 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 9.11 command a table 33 command a format command a loads control register 4 with data that determines the function of pin 2 (p04/acm(vob2)). table 34 selection of p04 or acm 9.12 commands b, c and d table 35 command b format table 36 command c format table 37 command d format these three commands determine the vertical and horizontal start positions of the display. 64 vertical and 64 horizontal start positions can be selected. after a master reset, starting positions are not guaranteed and therefore must be programmed by the user. the horizontal start position (hp) and the vertical start position (vp) may be calculated as follows: where (h5 ? h0) is the decimal value of these 6 bits and (h5 ? h0) 3 4. where (v5 ? v0) is the decimal value of these 6 bits and (v5 ? v0) 3 0. bs1bs076543210 0 1 01110a/p00 a/p pin function 0 p04 is selected as an output port. data is written to this port using command e. this is also the default setting. 1 acm function selected; can also be used as the 5th colour signal. bs1bs076543210 0 1 1 0 0 1 v5 v4 v3 v2 bs1bs076543210 0 1 1 0 1 0 v1 v0 h5 h4 bs1bs076543210 0 1 1 0 1 1 h3 h2 h1 h0 hp 4 h5 h0 ? () 5 + [] f osd = vp 4 v5 v0 ? () [] number of scan lines = 9.13 command e when output ports p00, p01 and p04 are enabled, command e is used to write data to them. table 38 command e format 9.14 command f table 39 command f format this command loads control register 5 with data that determines the background colour in frame shadowing mode. 9.15 command g table 40 command g format command g is used to enable/disable the osd horizontal stabilization circuit, to select the half-tone mode and to select the character size of the first line. in the half-tone mode, excellent semi-transparent half-tone effects can be obtained with osd frequencies in the range 4 to 7 mhz. this mode also enhances the background colour with intensity output. for further details on the half-tone effect refer to the the programming guide for the PCA8516 report number mict/an9402. table 41 horizontal stabilization circuit control table 42 selection of half-tone mode bs1 bs0 7 6 5 4 3 2 1 0 0 1 1 1 x p04 x x p01 p00 bs1bs076543210 0 0 0100rgbi bs1 bs0 7 6 5 4 3 2 1 0 0 0 0 1 0 1 hm3 ht2 fs1 fs0 hm3 state of stabilization circuit 0 stabilization circuit disabled (the default state). 1 horizontal stabilization circuit enabled. ht2 half-tone mode 0 half-tone mode not selected (the default state). 1 half-tone mode available when acm bit = 1.
1995 mar 30 36 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 table 43 selection of the character size for the ?rst line 10 miscellaneous 10.1 space and carriage return codes in different background/shadowing modes figures 30 to 34 show the space code and carriage return code in the 4 different background/shadowing modes: mode 0: the no background mode. both the space code and the carriage return code are displayed as transparent (no bit) patterns with the video signal as the background. this is shown in fig.30. mode 1: the north-west shadowing mode. both codes are displayed in the same manner as for mode 0. this is shown in fig.31. mode 2: the box shadowing mode. the space code is displayed as an opaque pattern with a selected background colour. this will also be the background colour of the character following the space code. the carriage return code however, is displayed as a transparent (no bit) pattern superimposed on the video signal. this is shown in fig.32. the space code can also be displayed as a transparent pattern on the video signal, and this is shown in fig.33. the choice of whether the space code displays an opaque pattern or a transparent pattern is mask programmable. mode 3: the frame shadowing mode. the space code and carriage return code are displayed as transparent patterns with background colour. this is shown in fig.34. fs1 fs0 character dot size 0 0 1h/1v (the default size) 0 1 2h/2v 1 0 3h/3v 1 1 4h/4v 10.2 combination of character font cells two (or more) character font cells may be combined in a horizontal or vertical direction to create a new higher resolution pattern. the combination of two cells in a horizontal direction is straight forward and requires no special precautions to be taken. when combining character cells in this manner all 4 background/shadowing modes are available. an example of combining two character font cells in a horizontal direction is shown in fig.35. however, the combination of two character font cells in a vertical direction is more difficult and care must be taken; otherwise, the new pattern may be created with gaps in its shadowing. an example of a character pattern with gaps is shown in fig.37. providing the steps listed below are followed no problems with shadowing will occur. the line spacing between two rows of characters must be programmed to 0h. this procedure is explained in section 9.3.2. if the north-west shadowing mode is selected then when combining two character cells in a vertical direction row 0 must contain the same bit pattern as held in row 18 of the character directly above it. this is shown in fig.38. if north-west shadowing is not required then row 0 should contain all zeros.
1995 mar 30 37 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.30 space code and carriage return code in no background mode - transparent pattern. handbook, full pagewidth sp code cr code red blue mra853 012345 67 891011 012345 67 891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 012345 67 891011 012345 67 891011
1995 mar 30 38 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.31 space code and carriage return code in north-west shadowing mode - transparent pattern. handbook, full pagewidth sp code cr code red blue black (background) green (background) mra854 012345 67 891011 012345 67 891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 012345 67 891011 012345 67 891011
1995 mar 30 39 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.32 space code and carriage return code in box shadowing mode. handbook, full pagewidth red blue cr code 012345 67 891011 012345 67 891011 yellow(background) cyan (background) sp code is an opaque pattern with the background colour of the character it intends to change or keep. cr code is always a transparent pattern with the video signal as its background. sp code can change the background colour of itself and the character/word next to it (in this example: from cyan to yellow). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 012345 67 891011 012345 67 891011 sp code mra855
1995 mar 30 40 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.33 space code and carriage return code in box shadowing mode. handbook, full pagewidth cr code 012345 67 891011 012345 67 891011 red blue yellow (background) cyan (background) sp code is an transparent pattern with no background colour. cr code is always a transparent pattern with the video signal as its background. sp code can change the background colour the character/word next to it (in this example : from cyan to yellow). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 012345 67 891011 012345 67 891011 sp code med267
1995 mar 30 41 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.34 space code and carriage return code in frame shadowing mode. handbook, full pagewidth red blue cr code yellow (background) sp code sp and cr codes are both transparent patterns coloured the same as the background colour. mra856 012345 67 891011 012345 67 891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 012345 67 891011 012345 67 891011
1995 mar 30 42 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.35 combination of two character cells in a horizontal direction to create a new font. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 mra849
1995 mar 30 43 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.36 combination of two character cells in a horizontal direction to create a new font north-west shadowing mode. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 mra850
1995 mar 30 44 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.37 combination of two characters in a vertical direction - with gap. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 cell boundary 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 18 if row 0 of the lower character does not contain the bit pattern of row 18 of the upper character in north west shadowing mode, a gap in the shadow might occur. mra851 character pattern displayed on the screen character pattern stored in the rom/ram
1995 mar 30 45 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.38 combination of two characters in a vertical direction - with no gap. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 cell boundary 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 18 row 0 of the lower character should contain the bit pattern of row 18 of the upper character in north west shadowing mode to avoid a 'break' in the shadow mra852 character pattern displayed on the screen character pattern stored in the rom/ram
1995 mar 30 46 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 11 osd clock the on-chip clock generator comprises phase-locked loop circuitry and is shown in fig.39. the frequency of the osd clock is programmable and is determined by the contents of the 6-bit counter, which is loaded using command 6. the osd clock frequency is calculated as shown below; frequencies within the range 4 to 14 mhz can be selected. where: 16 < (pllcn) < 40; (pllcn) is the decimal value held in the 6-bit counter. the voltage controlled oscillator (vco) is synchronized to the high-to-low edge of f 1 (see fig.39) which is always on the trailing edge of f hsync . the programmable active level detector will pass the hsync signal if it is programmed as active high or invert the hsync signal if it is programmed as active low. the 4-bit prescaler increments or decrements the output of the vco in steps of (16 f hsync ). f osd f hsync 16 pllcn () = the osd clock is enabled/disabled using command 7; see section 9.8. when the osd clock is disabled, the oscillator remains active, therefore the transient time from the osd clock start-up to locking into the external h sync signal is reduced. as the on-chip oscillator is always active after power-on, when the osd clock is enabled no large currents flow (as for rc or lc oscillators); therefore radiated noise is dramatically reduced. character width is a function of the osd clock frequency; decreasing f osd increases the width of the characters. therefore, for optimum character display quality the choice of the osd clock frequency is important; this is explained in chapter 12. fig.39 block diagram of osd oscillator. handbook, full pagewidth mlc349 voltage controlled oscillator charge pump and loop filter phase/ frequency detector active level detector programmable 6-bit counter f osd divided by n 4-bit prescaler hsync osd disable f pll f 1 c r 1 c 1
1995 mar 30 47 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 12 osd clock selection for different tv standards 12.1 osd frequency the PCA8516 supports four different tv scanning standards. to obtain the best quality character display, each tv standard requires a different osd frequency. to cater for this requirement the PCA8516 provides a programmable osd clock that generates frequencies in the range 4 to 14 mhz. the three examples given below illustrate the osd clock requirements for different tv scanning standards. 12.1.1 ntsc 525lpf/60 hz and pal 625lpf/50 hz the osd clock is applied directly to the osd circuitry and can take any value within the 4 to 14 mhz frequency range. the ntsc 525lpf/60 hz standard when used with a 19 inch screen and an osd clock of 8 mhz, produces a character dot width of 13.2 mm. 12.1.2 ntsc 1050lpf/60 hz with this standard, in order to obtain the same character dot width as in the ntsc 525lpf/60 hz standard that uses an osd clock of 7 mhz; the osd clock must be doubled to 14 mhz because the horizontal frequency is doubled. to keep the same character height as that in the ntsc 525lpf/60 hz standard, hsync is also divided by two, internally. 12.1.3 pal 1250lpf/100 hz with this standard, in order to obtain the same character dot width as in the pal 625lpf/50 hz standard; the osd clock must be doubled. hsync is applied directly to the osd circuitry without being divided by two as both the horizontal frequency (1250 hz) and the vertical frequency (100 hz) are doubled. 12.2 maximum number of characters per row the number of characters per row is a function of the osd clock frequency and the tv standard used. with reference to fig.40 the active video signal period of a horizontal line is 53.5 m s. however, in order to reduce jittering at the screen edge, overscan is normally applied by the tv manufacturer and this reduces the visible video signal period to 48.15 m s. the examples given below show how the number of characters per row and the character width may be obtained for the ntsc 525lpf/60 hz tv standard using different osd clock frequencies. 12.2.1 ntsc 525lpf/60 hz; f osd = 6 mhz as f osd = 6 mhz: t osd = 0.1666 m s. the number of visible dots on one horizontal line is 290 (48.15 m s/0.1666 m s). however, as the starting position of the first character dot is approximately 45 dots after hsync, the actual visible number of dots per line is 245. each character is composed of a 12 18 dot matrix; therefore the maximum number of characters on one line is 20 (245/12). if a 19 inch tv screen is used, the width of a horizontal line is approximately 370 mm and this gives a character width of 18.5 mm. 12.2.2 ntsc 525lpf/60 hz; f osd = 10 mhz as f osd = 10 mhz: t osd = 0.1 m s. the number of visible dots on one horizontal line is 481 (48.15 m s/0.1 m s). allowing for the initial starting position of 45 dots, the actual number of visible dots per line is 436. each character is composed of a 12 18 dot matrix; therefore the maximum number of characters on one line is 36. with a 19 inch tv screen, the width of a horizontal line is approximately 370 mm and the character width is 10.3 mm.
1995 mar 30 48 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 12.3 maximum number of rows per frame the number of rows per frame is a function of the number of active lines per display field and the number of vertical dots in the character matrix (which is 18). the number of rows per frame (n) is calculated as shown below. the four examples shown below illustrate how the maximum number of rows per frame is obtained for each tv scanning standard. 12.3.1 ntsc 525lpf/60 h z the number of active lines per field for this standard is between 241.5 and 249h (see fig.41). if the value of 241 is used then the maximum number of rows per frame is 13. 12.3.2 pal 625lpf/50 h z the number of active lines per field for this standard is 280. therefore, the maximum number of rows per frame is 15. 12.3.3 ntsc 1050lpf/60 h z for this standard the number of active lines per frame is double that of the ntsc 525lpf/60 hz standard. however, as hsync is divided by two internally, the maximum number of rows per frame is also 13. 12.3.4 pal 1250lpf/100 h z with this standard it is not necessary to divide hsync by two as both the horizontal and vertical frequency are doubled. the maximum number of rows per frame is 15. n number of active lines per field 18 -------------------------------------------------------------------------------- - =
1995 mar 30 49 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 handbook, full pagewidth mra862 blacker than black, 100% blanking level 75% black, 67.5 2.5% composite video signal 0 white, 12.5 2.5% right left 0 horizontal deflection sawtooth trace retrace begins retrace retrace ends blanking begins blanking ends fig.40 composite video signal for three horizontal lines compared to three horizontal deflection sawteeth (ntsc 525lpf/60 hz).
1995 mar 30 50 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 handbook, full pagewidth mra863 equalizing pulse interval vertical sync pulse interval equalizing pulse interval blacker than black black level white level zero carrier horizontal blanking picture bottom of picture vertical blanking 0.05 v 0.03 v 0 3h 3h 3h h hh 0.5 h h 0.5 h h 100% (75 2.5)% (12.5 2.5)% 0% start of next field first field, 262.5 h 16.666 s or 1/60 s second field, 262.5 h 16.666 s or 1/60 s vertical blanking period 13 to 21 h active lines 241.5 to 249.5 h vertical blanking period 13 to 21 h (825.5 to 1335.5 s) active lines 241.5 to 249.5 h right left horizontal deflection sawtooth trace trace vertical deflection sawtooth bottom top first field vertical deflection sawtooth blanking begins blanking ends retrace 500 to 750 s second field vertical deflection sawtooth retrace m m m m fig.41 vertical synchronization and blanking pulse intervals for one frame (ntsc 525lpf/60 hz).
1995 mar 30 51 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 13 output ports the three output ports p00, p01 and p04 can be configured using one of three mask options. the three output mask options are specified below: option 1 standard output with switched pull-up current source. see figs 42 and 45. option 2 open-drain output. see figs 43 and 46. option 3 push-pull output. see figs 44 and 47. the state of each output port after a power-on-reset can also be selected using the mask options. all the available mask options for the PCA8516 are given in section 13.1. fig.42 standard output with switched pull-up current source (option 1 - p00 and p01). handbook, full pagewidth dmq dsq sq write pulse data bus current source tr3 tr4 read pulse (testing use only) mbe128 v ss tr1 tr2 100 m a typical pin v dd port output register
1995 mar 30 52 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.43 open-drain output (option 2 - p00 and p01). handbook, full pagewidth d mq d sq sq write pulse data bus read pulse (testing use only) mbe129 v ss tr1 pin v dd port output register fig.44 push-pull output (option 3 - p00 and p01). handbook, full pagewidth dmq dsq sq write pulse data bus current source tr3 tr4 read pulse (testing use only) mbe130 v ss tr1 tr2 100 m a typical pin v dd port output register
1995 mar 30 53 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.45 standard output with switched pull-up current source (option 1 - p04). handbook, full pagewidth dmq dsq sq write pulse data bus current source tr3 tr4 read pulse (testing use only) mlb353 - 1 v ss tr1 tr2 100 m a typical pin v dd port output register acm output enable (a/p bit) acm output from osd circuit fig.46 open-drain output (option 2 - p04). handbook, full pagewidth dmq dsq write pulse data bus read pulse (testing use only) mlb354 - 1 v ss tr1 pin v dd port output register acm output enable (a/p bit) acm output from osd circuit
1995 mar 30 54 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 fig.47 push-pull output (option 3 - p04). handbook, full pagewidth dmq dsq write pulse data bus current source tr3 tr4 read pulse (testing use only) mlb355 - 1 v ss tr1 tr2 100 m a typical pin v dd port output register acm output enable (a/p bit) acm output from osd circuit
1995 mar 30 55 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 13.1 mask options tables 44 to 48 list the available mask options for the PCA8516. table 47 is intended for customer use when ordering the device. table 44 port con?guration options table 45 port state after power-on-reset table 46 space code options option port 1, 2 or 3 p00 1, 2 or 3 p01 1, 2 or 3 p04 option port high p00 high p01 high or low p04 option shadowing mode transparent pattern available in box shadowing mode only; see fig.33. opaque pattern available in box shadowing mode only; see fig.32. table 47 customer selected mask options feature option output port con?gurations p00 p01 p04 port state after power-on-reset p00 p01 p04 oscillator tranconductance low medium high space code pattern transparent opaque table 48 system oscillator transconductance options option transconductance (ms) f osc - quartz crystal (mhz) f osc - ceramic resonator (mhz) low 0.7 1 to 6 - medium 1.6 4 to 12 1 to 6 high 4.5 - 3to16
1995 mar 30 56 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 14 default values after power-on-reset the default values of registers after a power-on-reset are specified in table 49. all other settings must be initialized by the user after a power-on-reset. table 49 default values register bit state after reset description user directly controllable registers control register 1 m1 0 scanning mode selection bits. conventional ntsc 525lpf/60 hz and/or pal 625lpf/50 hz selected. m0 0 bp 1 polarity control bit; the output polarities of fb, acm, r, g, b and i are active high. en 0 osd enable/disable control bit; the osd is disabled. control register 2 hp 0 hsync input polarity control bit; the input polarity is active low. vp 0 vsync input polarity control bit; the input polarity is active low. s1 0 display mode selection bits; the north-west shadowing mode is selected. s0 1 control register 3 bf1 0 blinking frequency control bits. the blinking frequency is set to f vsync /16 hz. bf0 0 br1 0 active ratio of blinking frequency control bits. the active ratio is set to 3 : 1. br0 0 control register 4 a/p 0 port control bit. pin 2 (p04/acm/vob2) is selected as an output port pin. control register 5 r 0 background colour selection bits in frame shadowing mode; the default colour is blue. g0 b1 i0 - bs1 0 command bank selection bits. command bank 00 is selected. bs0 0 user indirectly controllable registers acm acm 0 the acm output is low unless changed by the space code. background colour b 1 the background colour selected is blue unless changed by the space code. r0 g0 i0 character size t4 0 the default character size is 1v/1h. a different value can be selected by using the carriage return code. t3 0 end of display t0 0 will continue to display next character (if the osd clock is enabled).
1995 mar 30 57 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 15 limiting values in accordance with the absolute maximum rating system (iec 134). symbol parameter min. max. unit v dd supply voltage - 0.5 +7.0 v v i all input voltages - 0.5 v dd + 0.5 v i oh maximum source current for all port lines -- 5.0 ma i ol maximum sink current for all port lines - 5.0 ma p tot total power dissipation - 500 mw t stg storage temperature - 55 +125 c t amb operating ambient temperature - 20 +70 c
1995 mar 30 58 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 16 dc characteristics v dd =5v 10%; v ss =0v; t amb = - 20 to +70 c. all voltages with respect to v ss unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit v dd operating supply voltage 4.5 5.0 5.5 v i dd operating supply current v dd =5v; f xtal = 3 mhz; f osd =10mhz - 510 ma v dd =5v; f xtal = 3 mhz; f osd = stop - 714 ma v dd =5v; f xtal = 3 mhz; f osd = stop - 12 ma reset, test1, test2, hsync, vsync, e and hio/ i 2 c inputs v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v i li input leakage current v ss < v i < v dd 0.01 0.20 10 m a ports p00 to p03 (with combined functions) inputs v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v i li input leakage current v ss < v i < v dd -- 10 m a ports p00 to p03 (with combined functions) outputs i ol low level output sink current v dd =5v; v o = 0.4 v 5.0 12.0 - ma i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5v; v o =v dd - 0.4 v - 3.0 - 7.0 - ma sda/sin and sck/sclk inputs v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v sda/sin and sck/sclk outputs i ol low level open drain sink current v dd =5v; v o = 0.4 v 3.0 -- ma r, g, b, i, fb and p04/acm outputs i ol low level push-pull output sink current v dd =5v; v o = 0.4 v 3.2 5.5 - ma i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5v; v o =v dd - 0.4 v - 1.6 - 2.4 - ma
1995 mar 30 59 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 17 ac characteristics v dd =5v 10%, v ss =0v. note 1. the minimum frequency should be 3 times greater than the maximum i 2 c-bus frequency or the hio frequency used in the system. symbol parameter conditions min. typ. max. unit f xtal crystal oscillator frequency note 1 0.5 3.0 6.0 mhz f osd osd oscillator frequency 1v/1h scanning mode 4.0 7.0 10.0 mhz 1v/2h and 2v/2h scanning modes 4.0 12.0 14.0 mhz c osd external capacitance at pin c 0.4 - 4.0 m f r osd external resistance at pin c 5.0 - 15.0 k w
1995 mar 30 60 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 18 package outlines unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot234-1 92-11-17 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 22.3 21.4 9.1 8.7 3.2 2.8 0.18 1.778 10.16 10.7 10.2 12.2 10.5 1.6 4.7 0.51 3.8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 24 1 13 12 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip24: plastic shrink dual in-line package; 24 leads (400 mil) sot234-1
1995 mar 30 61 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot137-1 x 12 24 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a 13 (a ) 3 a y 0.25 075e05 ms-013ad pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.61 0.60 0.30 0.29 0.050 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 e 1 0 5 10 mm scale so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1 95-01-24 97-05-22
1995 mar 30 62 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 19 soldering 19.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 19.2 dip 19.2.1 s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 19.2.2 r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 19.3 so 19.3.1 r eflow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 19.3.2 w ave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.3.3 r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1995 mar 30 63 philips semiconductors preliminary speci?cation stand-alone osd PCA8516 20 definitions 21 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 22 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
philips semiconductors philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40 783 749, fax. (31)40 788 399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil. p.o. box 7383 (01064-970). tel. (011)821-2333, fax. (011)829-1849 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032)88 2636, fax. (031)57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (9)0-50261, fax. (9)0-520971 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: p.o. box 10 63 23, 20043 hamburg, tel. (040)3296-0, fax. (040)3296 213. greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 hong kong: philips hong kong ltd., 15/f philips ind. bldg., 24-28 kung yip st., kwai chung, n.t., tel. (852)424 5121, fax. (852)480 6960/480 6009 india: philips india ltd, shivsagar estate, a block , dr. annie besant rd. worli, bombay 400 018 tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)640 000, fax. (01)640 200 italy: philips semiconductors s.r.l., piazza iv novembre 3, 20124 milano, tel. (0039)2 6752 2531, fax. (0039)2 6752 2557 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5028, fax. (03)3740 0580 korea: (republic of) philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)794-5011, fax. (02)798-8022 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb tel. (040)783749, fax. (040)788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546. philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366. singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382. thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319. turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 2770, fax. (0212)282 6707 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd38 ? philips electronics n.v. 1995 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 453061/1500/01/pp64 date of release: 1995 mar 30 document order number: 9397 750 00024

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